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? semiconductor components industries, llc, 2012 february, 2012 ? rev. 0 1 publication order number: ncp4624/d ncp4624 150 ma, wide input range, ldo linear voltage regulator the ncp4624 is a cmos 150 ma ldo linear voltage regulator which features high input voltage range while maintaining low quiescent current 2 a typically. several protection features like current limiting and reverse current protection circuit are fully integrated to create a versatile device suitable for the power source being in the standby ? mode. a high maximum input voltage (11 v) and wide temperature range ( ? 40 c to 85 c) makes the ncp4624 device with output capacitor as low as 0.1 f an ideal choice for industrial applications also a portable equipments powered by 2 ? cell li ? ion battery. features ? operating input voltage range: 2.5 v to set v out + 6.5 v, max. 11 v ? output voltage range: 1.2 to 5.5 v (available in 0.1 v steps) ? 2% output voltage accuracy ? output current: min. 150 ma ? line regulation: 0.02%/v ? current limit circuit ? available in sot ? 23 ? 5, udfn 1.0 x 1.0 mm and sc ? 88a package ? built ? in reverse current protection circuit ? these are pb ? free devices typical applications ? home appliances, industrial equipment ? cable boxes, satellite receivers, entertainment systems ? car audio equipment, navigation systems ? notebook adaptors, lcd tvs, cordless phones and private lan systems ? battery ? powered portable communication equipments vin vout ce gnd c1 c2 vin vout ncp4624x figure 1. typical application schematic 0.1 f 0.1 f http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 15 of this data sheet. ordering information xx, xxx, xxxx = specific device code m, mm = date code a = assembly location y = year w = work week = pb ? free package marking diagrams (*note: microdot may be in either location) udfn4 case 517br sot ? 23 ? 5 case 1212 1 xx mm 1 sc ? 88a (sc ? 70 ? 5/sot ? 353) case 419a xxxx m 1 xxxmm 1
ncp4624 http://onsemi.com 2 current limit vin gnd vref ce vout reverse detector ncp4624xxxx current limit vin gnd vref ce vout reverse detector ncp4624dxx figure 2. simplified schematic block diagram pin function description pin no. pin name description sot ? 23 ? 5 sc ? 88a udfn 1x1 1 5 4 vin input pin 2 3 2 gnd ground pin 3 1 3 ce chip enable pin (?h? active) 4 2 nc non connected 5 4 1 vout output pin *ep ep exposed pad (leave floating or connect to gnd) absolute maximum ratings rating symbol value unit input voltage (note 1) v in ? 0.3 to 12 v output voltage v out ? 0.3 to v in 11 v chip enable input v ce ? 0.3 to v in 11 v power dissipation sot ? 23 ? 5 p d 420 mw power dissipation udfn 1.0 x 1.0 mm 400 power dissipation sc ? 88a 380 junction temperature t j ? 40 to 150 c storage temperature t stg ? 55 to 125 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating tested per jedec standard: jesd78.
ncp4624 http://onsemi.com 3 thermal characteristics rating symbol value unit thermal characteristics, sot ? 23 ? 5 thermal resistance, junction ? to ? air r ja 238 c/w thermal characteristics, udfn 1x1 thermal resistance, junction ? to ? air r ja 250 c/w thermal characteristics, sc ? 88a thermal resistance, junction ? to ? air r ja 263 c/w electrical characteristics ? 40 c t a 85 c; c in = c out = 0.1 f, unless otherwise noted. typical values are at t a = +25 c. parameter test conditions symbol min typ max unit operating input voltage 1.2 v < v out < 4.5 v v in 2.5 vset + 6.5 v 4.5 v v out < 5.5 v 11 output voltage ta = 25 c, v out > 1.5 v v out x0.99 x1.01 v ? 40 c < t a < 85 c, v out > 1.5v x0.982 x1.018 t a = 25 c, v out < 1.5 v ? 15 +15 mv ? 40 c < t a < 85 c, v out < 1.5v ? 28 +28 output voltage temp. coefficient v in = v out + 2 v, i out = 100 a, t a = ? 40 to 105 c 100 ppm/ c line regulation set v out + 0.5 v < v in < v in max, i out = 1 ma line reg 0.02 0.20 %/v load regulation v in = v out + 2 v, 0.1ma < i out 150 ma load reg ? 35 ? 3 35 mv dropout voltage i out = 150 ma 1.2 v v out < 1.3 v v do 1.68 2.59 v 1.3 v v out < 1.5 v 1.63 2.49 1.5 v v out < 1.8 v 1.48 2.23 1.8 v v out < 2.3 v 1.16 2.19 2.3 v v out < 3.0 v 0.90 1.47 3.0 v v out < 4.0 v 0.61 1.05 4.0 v v out 5.5 v 0.39 0.76 output current i out 150 ma short current limit v out = 0 v i sc 45 ma quiescent current iout = 0 ma i q 2.0 3.7 a standby current v in = v in max , v ce = 0 v i stb 0.2 0.6 a ce pin pull ? down current i pd 0.3 0.9 a ce pin threshold voltage ce input voltage ?h? v ceh 1.7 v in v ce input voltage ?l? v cel 0 0.8 reverse current 0 v v in < 11 v, v out > 1.5 v i rev 0 0.16 a reverse current detection offset 0 v v in < 11 v, v out > 1.5 v v rev_det 55 100 mv reverse current release offset 0 v v in < 11 v, v out > 1.5 v v rev_rel 70 120 mv power supply rejection ratio v in = v out + 2.5 v, v in_pk ? pk = 0.3 v, i out = 50 ma, f = 1 khz v out = 1.2 v psrr 27 db v out = 2.5 v 22 v out = 3.3 v 18 v out = 5.5 v 15 output noise voltage v out = 1.2 v, i out = 30 ma, f = 100 hz to 100 khz v noise 105 v rms autodischarge nmos resist- ance v in = 7.0 v, v ce = 0.0 v (d version only) r dson 380
ncp4624 http://onsemi.com 4 typical characteristics 1.4 1 1.2 0.6 0.8 0.4 0 0 50 100 150 200 250 300 350 400 0.2 0 50 100 150 200 250 300 350 400 i out (ma) v out (v) v in = 2.5 v 5.5 v figure 3. output voltage vs. output current 1.2 v version (t j = 25 c) 4.0 v 7.5 v 0 0.5 1 1.5 2 2.5 3 3.5 0 50 100 150 200 250 300 350 400 i out (ma) figure 4. output voltage vs. output current 3.3 v version (t j = 25 c) v out (v) 5.8 v 4.3 v v in = 9.8 v 5 6 4 2 3 1 0 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 i out (ma) figure 5. output voltage vs. output current 5.5 v version (t j = 25 c) v in = 6.5 v 11 v v out (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 01234567 v in (v) v out (v) i out = 50 ma 30 ma 1 ma figure 6. output voltage vs. input voltage 1.2 v version 3.5 4 3 2 2.5 1 1.5 0 0.5 0123 5678910 4 v out (v) v in (v) figure 7. output voltage vs. input voltage 3.3 v version i out = 50 ma 30 ma 1 ma 0 1 2 3 4 5 6 7 01234567891011 v in (v) v out (v) figure 8. output voltage vs. input voltage 5.5 v version i out = 50 ma 30 ma 1 ma
ncp4624 http://onsemi.com 5 typical characteristics 1.18 1.19 1.2 1.21 1.22 ? 40 ? 200 20406080 t j , junction temperature ( c) v out (v) figure 9. output voltage vs. temperature, 1.2 v version 3.27 3.28 3.29 3.3 3.31 3.32 3.33 ? 40 ? 200 20406080 t j , junction temperature ( c) v out (v) figure 10. output voltage vs. temperature, 3.3 v version 5.45 5.46 5.47 5.48 5.49 5.5 5.51 t j , junction temperature ( c) v out (v) figure 11. output voltage vs. temperature, 5.5 v version ? 40 ? 200 20406080 2 1.2 1.6 0.8 0 0.4 01234 678 5 v in (v) quiescent current ( a) figure 12. quiescent current vs. input voltage, 1.2 v version 0 0.5 1 1.5 2 2.5 012345678910 v in (v) quiescent current ( a) figure 13. quiescent current vs. input voltage, 3.3 v version 0 0.5 1 1.5 2 2.5 024681012 v in (v) quiescent current ( a) figure 14. quiescent current vs. input voltage, 5.5 v version
ncp4624 http://onsemi.com 6 typical characteristics 0 0.4 0.8 1.2 1.6 2 i out (ma) dropout voltage (v) figure 15. dropout voltage vs. output current, 1.2 v version 0 30 60 90 120 150 t a = 25 c t a = ? 40 c t a = 85 c 0 0.2 0.4 0.6 0.8 0 30 60 90 120 150 i out (ma) figure 16. dropout voltage vs. output current, 3.3 v version dropout voltage (v) t a = 25 c t a = 85 c t a = ? 40 c 0 0.1 0.2 0.3 0.4 0.5 0 30 60 90 120 150 i out (ma) dropout voltage (v) figure 17. dropout voltage vs. output current, 5.5 v version t a = 25 c t a = ? 40 c t a = 85 c 0 1 2 3 4 5 6 frequency (hz) figure 18. output voltage noise, 1.2 v version, v in = 2.5 v, i out = 30 ma, c in = c out = 0.1 f v n , output voltage noise ( v rms / hz ) 10 100 1k 10k 100k 1m 0 2 4 6 8 10 12 frequency (hz) figure 19. output voltage noise, 3.3 v version, v in = 4.3 v, i out = 30 ma, c in = c out = 0.1 f v n , output voltage noise ( v rms / hz ) 0 2 4 6 8 10 12 14 frequency (hz) figure 20. output voltage noise, 5.5 v version, v in = 6.5 v, i out = 30 ma, c in = c out = 0.1 f v n , output voltage noise ( v rms / hz ) 10 100 1k 10k 100k 1m 10 100 1k 10k 100k 1m
ncp4624 http://onsemi.com 7 typical characteristics 0 10 20 30 40 50 60 70 figure 21. psrr vs. frequency, 1.2 v version psrr (db) frequency (hz) i out = 50 ma 1 ma 30 ma 30 40 50 60 0 10 20 figure 22. psrr vs. frequency, 3.3 v version psrr (db) frequency (hz) 1 ma 30 ma i out = 50 ma 30 40 50 60 0 10 20 figure 23. psrr vs. frequency, 5.5 v version psrr (db) frequency (khz) i out = 50 ma 1 ma 30 ma 2.5 3.0 3.5 4.0 1.2 1.4 1.6 1.8 0.6 0.8 1.0 figure 24. line transients, 1.2 v version, i out = 1 ma v out (v) t (ms) v in (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 10 100 1k 10k 100k 1m 10 100 1k 10k 100k 1m 10 100 1k 10k 100k 1m
ncp4624 http://onsemi.com 8 typical characteristics 4.3 4.8 5.3 5.8 3.3 3.5 3.7 3.9 2.7 2.9 3.1 figure 25. line transients, 3.3 v version, i out = 1 ma v out (v) t (ms) v in (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 6.5 7.0 7.5 8.0 5.5 5.7 5.9 6.1 4.9 5.1 5.3 figure 26. line transients, 5.5 v version, i out = 1 ma v out (v) t (ms) v in (v) 0 40 80 120 160 200 240 280 320 360 400 0 5 10 15 1.2 1.4 1.6 1.8 0.6 0.8 1.0 figure 27. load transients, 1.2 v version, load step 1 ma to 10 ma, v in = 2.5 v v out (v) t ( s) i out (ma) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ncp4624 http://onsemi.com 9 typical characteristics 0 5 10 15 3.3 3.5 3.7 3.9 2.7 2.9 3.1 figure 28. load transients, 3.3 v version, load step 1 ma to 10 ma, v in = 4.3 v v out (v) t ( s) i out (ma) 0 40 80 120 160 200 240 280 320 360 400 0 5 10 15 5.5 5.7 5.9 6.1 4.9 5.1 5.3 figure 29. load transients, 5.5 v version, load step 1 ma to 10 ma, v in = 6.5 v v out (v) t ( s) i out (ma) 0 40 80 120 160 200 240 280 320 360 400 0 50 100 150 1.2 1.6 2.0 2.4 0.0 0.4 0.8 figure 30. load transients, 1.2 v version, load step 50 ma to 100 ma, v in = 2.5 v v out (v) t ( s) i out (ma) 0 40 80 120 160 200 240 280 320 360 400
ncp4624 http://onsemi.com 10 typical characteristics 0 50 100 150 2.1 2.5 2.9 3.3 3.7 4.1 4.5 0 40 80 120 160 200 240 280 320 360 400 figure 31. load transients, 3.3 v version, load step 50 ma to 100 ma, v in = 4.3 v v out (v) t ( s) i out (ma) 4.3 4.7 5.1 5.5 5.9 6.3 6.7 0 50 100 150 0 40 80 120 160 200 240 280 320 360 400 figure 32. load transients, 5.5 v version, load step 50 ma to 100 ma, v in = 6.5 v v out (v) t ( s) i out (ma) 0.0 1.5 3.0 4.5 ? 0.3 0.0 0.3 0.6 0.9 1.2 0 40 80 120 160 200 240 280 320 360 400 figure 33. turn ? on behavior, 1.2 version, v in = 3 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma
ncp4624 http://onsemi.com 11 typical characteristics 0.0 2.2 4.4 6.6 1.0 0.0 1.0 2.0 3.0 4.0 0 40 80 120 160 200 240 280 320 360 400 figure 34. turn ? on behavior, 3.3 version, v in = 4.3 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma 0.00 3.25 6.50 9.75 ? 1.5 0.0 1.5 3.0 4.5 6.0 0 40 80 120 160 200 240 280 320 360 400 figure 35. turn ? on behavior, 5.5 version, v in = 6.5 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma 0.0 1.5 3.0 4.5 ? 0.3 0.0 0.3 0.6 0.9 1.2 0 40 80 120 160 200 240 280 320 360 400 figure 36. turn ? off behavior, 1.2 version, v in = 3 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma
ncp4624 http://onsemi.com 12 typical characteristics 0.0 2.2 4.4 6.6 ? 1.0 0.0 1.0 2.0 3.0 4.0 0 40 80 120 160 200 240 280 320 360 400 figure 37. turn ? off behavior, 3.3 version, v in = 4.3 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma 0.00 3.25 6.50 9.75 ? 1.5 0.0 1.5 3.0 4.5 6.0 0 40 80 120 160 200 240 280 320 360 400 figure 38. turn ? off behavior, 5.5 version, v in = 6.5 v v out (v) v ce (v) t ( s) chip enable i out = 1 ma i out = 30 ma i out = 150 ma
ncp4624 http://onsemi.com 13 application information a typical application circuit for ncp4624 series is shown in the figure 39. vin vout ce gnd c1 c2 vin vout ncp4624x figure 39. typical application schematic 0.1 f 0.1 f input decoupling capacitor (c1) a 100 nf ceramic input decoupling capacitor should be connected as close as possible to the input and ground pin of the ncp4624. higher values and lower esr improves line transient response. output decoupling capacitor (c2) a 100 nf ceramic output decoupling capacitor is sufficient to achieve stable operation of the ic. if tantalum capacitor is used, and its esr is high, the loop oscillation may result. the capacitor should be connected as close as possible to the output and ground pin. larger values and lower esr improves dynamic parameters. enable operation the enable pin ce may be used for turning the regulator on and off. the ic is switched on when a high level voltage is applied to the ce pin. the enable pin has an internal pull down current source which assure off state of ldo in case the ce pin will stay floating. if the enable function is not needed connect ce pin to vin. the d version of the ncp4624 includes a transistor between vout and gnd that is used for faster dischar ging of the output capacitor. this function is activated when the ic goes into disable mode. thermal consideration as a power across the ic increase, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and also the ambient temperature affect the rate of temperature increase for the part. when the device has good thermal conductivity through t he pcb the junction temperature will be relatively low in high power dissipation applications. reverse current protection circuit internal reverse current circuitry stops the reverse current from vout pin to gnd pin and vin pin when v out goes higher than v in voltage or v set voltage. v set means voltage given by voltage version. the parasitic diode of pmos pass device is internally switched to reverse direction before v in becomes lower than v out . the operation coverage of the reverse current protection circuit is v out > 1.5 v. in order to avoid unstable behavior a hysteresis is created by different threshold of detecting voltage v rev_det and releasing voltage v rev_rel . see figures 40 and 41 for details of configuration. current limit vin gnd vref ce vout reverse detector current limit vin gnd vref ce vout reverse detector figure 40. normal operating mode figure 41. reverse current protection mode
ncp4624 http://onsemi.com 14 esr versus output current when using the ncp4624 devices, consider the following points: ? the relation between output current i out and esr of the output capacitor are shown below in figures 42, 43 and 44. ? the conditions when the device performs stable operation are marked as the hatched area in the charts. figure 42. esr vs. load current figure 43. esr vs. load current figure 44. esr vs. load current ncp4624xxx12xx, v in = 2.5 v, c in = c out = 0.1 f, t a = 25 c ncp4624xxx33xx, v in = 4.3 v, c in = c out = 0.1 f, t a = 25 c ncp4624xxx55xx, v in = 6.5 v, c in = c out = 0.1 f, t a = 25 c
ncp4624 http://onsemi.com 15 ordering information device marking nominal output voltage feature package shipping ncp4624dmu12tcg 5a 1.2 v enable high, dfn1010 (pb ? free) 10000 / tape & reel auto discharge ncp4624dmu30tcg 5x 3.0 v enable high, dfn1010 (pb ? free) 10000 / tape & reel auto discharge ncp4624dmu33tcg 6a 3.3 v enable high, dfn1010 (pb ? free) 10000 / tape & reel auto discharge ncp4624dmu50tcg 6t 5.0 v enable high, dfn1010 (pb ? free) 10000 / tape & reel auto discharge ncp4624dsn12t1g f12 1.2 v enable high, sot ? 23 ? 5 (pb ? free) 3000 / tape & reel auto discharge ncp4624dsn18t1g f18 1.8 v enable high, sot ? 23 ? 5 (pb ? free) 3000 / tape & reel auto discharge ncp4624dsn33t1g f31 3.3 v enable high, sot ? 23 ? 5 (pb ? free) 3000 / tape & reel auto discharge ncp4624dsn50t1g f50 5.0 v enable high, sot ? 23 ? 5 (pb ? free) 3000 / tape & reel auto discharge NCP4624DSQ12T1G at12 1.2. v enable high, sc ? 88a (pb ? free) 3000 / tape & reel auto discharge ncp4624dsq33t1g at33 3.3 v enable high, sc ? 88a (pb ? free) 3000 / tape & reel auto discharge ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp4624 http://onsemi.com 16 package dimensions sot ? 23 5 ? lead case 1212 ? 01 issue a dim min max millimeters a1 0.00 0.10 a2 1.00 1.30 b 0.30 0.50 c 0.10 0.25 d 2.70 3.10 e 2.50 3.10 e1 1.50 1.80 e 0.95 bsc l l1 0.45 0.75 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. datum c is the seating plane. a 1 5 23 4 d e1 b l1 e e c m 0.10 c s b s a b 5x a2 a1 s 0.05 c l 0.20 --- *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.95 dimensions: millimeters pitch 5x 3.30 0.56 5x 0.85 a --- 1.45 recommended a
ncp4624 http://onsemi.com 17 package dimensions udfn4 1.0x1.0, 0.65p case 517br ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 bottom view b e 4x note 3 2x 0.05 c pin one reference top view 2x 0.05 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 3x 1 2 dim min max millimeters a ??? 0.60 a1 0.00 0.05 a3 0.10 ref b 0.20 0.30 d 1.00 bsc d2 0.43 0.53 e 1.00 bsc e 0.65 bsc l 0.20 0.30 l2 0.27 0.37 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. mounting footprint* detail a 1.30 0.30 0.53 4x dimensions: millimeters 0.52 2x recommended package outline l2 detail a l3 detail b l3 0.02 0.12 detail b note 4 e/2 d2 45 a m 0.05 b c 4 3 0.65 pitch 4x typ c 0.18 0.23 4x 0.43 3x 0.10 3x
ncp4624 http://onsemi.com 18 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 419a ? 01 obsolete. new standard 419a ? 02. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. dim a min max min max millimeters 1.80 2.20 0.071 0.087 inches b 1.15 1.35 0.045 0.053 c 0.80 1.10 0.031 0.043 d 0.10 0.30 0.004 0.012 g 0.65 bsc 0.026 bsc h --- 0.10 --- 0.004 j 0.10 0.25 0.004 0.010 k 0.10 0.30 0.004 0.012 n 0.20 ref 0.008 ref s 2.00 2.20 0.079 0.087 b 0.2 (0.008) mm 12 3 4 5 a g s d 5 pl h c n j k ? b ? sc ? 88a (sc ? 70 ? 5/sot ? 353) case 419a ? 02 issue k on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp4624/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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